1. Field of the Invention
The present invention relates to a wafer probing test machine for examining device patterns formed on a semiconductor wafer in the course of manufacturing semiconductor devices such as LSIs and, more particularly, it relates to a system for positioning electrode pads on a semiconductor chip relative to probes.
2. Description of the Related Art
The wafer test which is intended to test the electric characteristic of each device pattern on the semiconductor wafer is conducted at the final stage of preparing the wafer because the cost of this test becomes extremely high if it is conducted after the process of dicing semiconductor chips from the wafer. The wafer test is aimed at eliminating defective devices in the course of preparing the wafers and feeding back test results to the previous processes to enhance productivity and reliability of semiconductor devices thus produced.
As disclosed in U.S. Pat. Nos. 4,875,005 and 4,965,515, the wafer test system of this type comprises fundamentally a wafer probing test machine and a tester. Both of them are connected to each other by measuring lines, wherein probes are contacted with bonding pads on the device pattern and test complete and fail signals are exchanged between the machine and the tester when the test is started through control lines. It is needed in this wafer probing test machine that the ultra-small bonding pads are positioned relative to the probes before the test so as to surely contact the probes with the bonding pads.
In the case of the conventional machine, a wafer stage 5 is moved in directions X, Y, Z and .theta. to position a chip 3, which is to be tested, just under an opening 6a of a probe card 6. The stage 5 is then lifted to contact tips of probes 7 with pads 4 on the chip 3 of the semiconductor wafer, as shown in FIG. 1.
The pads 4 are positioned relative to the probes 7 while viewing from just above those points at which the probes 7 are contacted with the pads 4 through a microscope 8 during the alignment (teaching) process, as shown in FIG. 2. The positioning of the pads relative to the probes is also sometimes carried out by marking needle tracks on the tops of the pads 4 by the probes 7 and viewing these needle tracks on the pads 4.
However, the semiconductor devices have been more and more highly integrated these days to have 16 and then 64 megabits. As they are highly integrated in this manner, the area of each pad 4 becomes smaller, numerous and the pitch at which the pads are arranged on the chip also becomes smaller Although the probe 7 is ultra-finely processed, the diameter of its tip is still 40 microns minimum. In the case of super LSIs which have 16 and 64 megabits, however, the number of pads formed on the chip amounts to more than several hundreds and the length of one side of the pad is extremely small, ranging from 40 to 60 microns. The tip of the probe 7, therefore, hides each pad 4 at the time when they are contacted with each other, thereby making it difficult to confirm the pads 4 in the view of the microscope.
This makes it difficult to confirm in the view of the microscope whether or not the probes 7 are fully contacted with the pads 4 at predetermined correct positions. In the case of the so-called bump pads, it is difficult to mark needle tracks on their tops. This makes it more difficult to confirm whether or not the probes are contacted with them. In the case of the semiconductor wafers on which patterns of the super LSIs having 16 and 64 megabits are formed, therefore, constant test results cannot be obtained, thereby making the reliability of the test low and the productivity of the semiconductor devices low, too.